A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to implement vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes transistor/memory-cell pillars extending through openings in repeating conducting/insulating structures films (e.g., tiers), where the conducting structures function as control gates. The vertically stacked tiers of conductive structures (e.g., word line plates, control gate plates) and insulating structures at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming a so-called “staircase” structure having so-called “stairs” at edges (e.g., lateral ends) of the tiers of conductive structures. The stairs are formed by etching exposed region of the conductive structures. The individual stairs define contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures. Various processes of forming staircase structures have been developed.
In one such fabrication process, a slot is formed in the alternating conductive structures and insulating structures before forming the staircase structure. Alternating conductive structures and insulating structures 2 are formed on a substrate (not shown) and a slot 14 is formed in the center of at least a portion of the alternating conductive structures and insulating structures 2, as shown in FIG. 1. For simplicity, the alternating conductive structures and insulating structures 2 are shown in FIG. 1 as a single material. The slot 14 extends from an uppermost surface of the alternating conductive structures and insulating structures 2 and into the alternating conductive structures and insulating structures 2 to a depth D1. The slot 14 also has a length L1 and a width W1. The slot 14 is defined by sidewalls 15 of the conductive structures and insulating structures 2 and a bottom surface 17 of the conductive structures and insulating structures 2. The sidewalls 15 are substantially vertical surfaces of exposed portions of the conductive structures and insulating structures 2 within the slot 14. The portion of alternating conductive structures and insulating structures 2 has a length L2 and a width W2.
A photoresist 18 is formed over the uppermost surface of the conductive structures and insulating structures 2 laterally adjacent to the slot 14, and over the sidewalls 15 and the bottom surface 17 of the alternating conductive structures and insulating structures 2 within the slot 14, as shown in FIG. 2. The photoresist 18, thus, contacts the sidewalls 15 of the conductive structures and insulating structures 2. Due to the large volume of photoresist 18 used and shrinkage in the photoresist 18 during and after its formation, delamination may occur at the sidewalls 15. The delamination may also be caused by poor adhesion between the photoresist 18 and the alternating conductive structures and insulating structures 2. As also shown in FIG. 2, because of the delamination, a so-called “creek” 19 may form along the bottom region of the sidewalls 15 of the slot 14 formed in the alternating conductive structures and insulating structures 2. Although not shown in FIG. 2 for simplicity, the creek 19 may also form throughout the sidewalls 15 of the slot 14 formed in the alternating conductive structures and insulating structures 2. A scanning electron micrograph (SEM) showing the photoresist 18 delaminating from the sidewalls 15 of the alternating conductive structures and insulating structures 2 is shown in FIG. 3.
As shown in FIG. 4A, a portion of the photoresist 18 is removed (e.g., etched, trimmed) by conventional photolithography techniques, such as by a dry etch process, to form an opening 21 in the photoresist 18. The opening 21 exposes vertical surfaces 22 of the photoresist 18. The exposure, bake, and development acts involved in the dry etch process may cause the photoresist 18 to shrink further, widening the creek 19 to form a void 23 between the sidewalls 15 of the alternating conductive structures and insulating structures 2 and the photoresist 18. The etchants of the dry etch process may enter the creek 19, widening the creek 19 and forming the void 23. The creek 19 may be enclosed within the bulk of the photoresist 18/sidewall 15 interface and may not be visible during non-destructive imaging. FIG. 4B shows the creek 19 visible at the photoresist 18/sidewall 15 interface as it extends up to the surface 22. During the subsequent dry etch process, the conductive structures and insulating structures 2 exposed by the opening 21 are etched vertically and the photoresist 18 is trimmed, causing surface 22 to move laterally and causing the opening 21 to widen. The repeating etch-trim processes creates multiple “stair” like steps in the alternating conductive structures and insulating structures 2, which results in the “staircase” structure. Under the plasma conditions of the dry etch process during the staircase formation, the etchants/reaction byproducts of the etch may enter (e.g., fill) the creek 19, etching the photoresist 18 in the creek 19, continuously widening the creek 19, and forming the void 23, shown in FIG. 5. Stairs subsequently formed adjacent to the void 23 have the same profile of the photoresist 18, which results in the formation of deformed stairs in the staircase structure. The void 24 results in deformation (e.g., change) in the profile of the portion of photoresist surface 22 adjacent to the sidewalls 15. A portion of stairs subsequently formed adjacent to the sidewall 15 have the same deformed profile projected from the deformed photoresist surface 22, which results in the formation of deformed stair region 28 in the staircase structure. An SEM of the resulting staircase structure 25 is shown in FIGS. 5A and 5B, with a region including the deformed stairs circled and the void 23 shown. Since the stairs have the undesired deformed profile which is not consistent in shape, contact structures (not shown) subsequently formed on these stairs are not properly aligned, causing failure of a device including the staircase structure. In other words, the contact structures land unreliably on the incorrect conductive plates, causing the device failure. To avoid device failure, changes to the fabrication process have been made. However, these changes add considerable expense and time to the fabrication process.